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a blackfin and the blackfin logo are registered trademarks of analog devices, inc. blackfin ? embedded processor adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features up to 600 mhz high performance blackfin processor two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of pro- gramming and compiler-friendly support advanced debug, trace, and performance monitoring 0.8 v to 1.2 v core v dd with on-chip voltage regulation 3.3 v and 2.5 v tolerant i/o 160-ball mini-bga, 169-ball lead free pbga, and 176-lead lqfp packages memory up to 148k bytes of on-chip memory: 16k bytes of instruction sram/cache 64k bytes of instruction sram 32k bytes of data sram/cache 32k bytes of data sram 4k bytes of scratchpad sram two dual-channel memory dma controllers memory management unit providing memory protection external memory controller with glueless support for sdram, sram, flash, and rom flexible memory booting opti ons from spi and external memory peripherals parallel peripheral interface (ppi)/gpio, supporting itu-r 656 video data formats two dual-channel, full duplex synchronous serial ports, sup- porting eight stereo i 2 s channels 12-channel dma controller spi compatible port three timer/counters with pwm support uart with support for irda ? event handler real-time clock watchdog timer debug/jtag interface on-chip pll capable of 1x to 63x frequency multiplication core timer figure 1. function al block diagram voltage regulator dma controller event controller/ core timer real-time clock uart port irda? timer0, timer1, timer2 ppi / gpio serial ports (2) spi port external port flash, sdram control boot rom jtag test and emulation watchdog timer l1 instruction memory l1 data memory mmu core / system bus interface b
rev. 0 | page 2 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 table of contents general description ................................................. 3 portable low power architecture ............................. 3 system integration ................................................ 3 adsp-bf531/2/3 processor peripherals .. ................... 3 blackfin processor core .......................................... 3 memory architecture ............................................ 4 dma controllers .................................................. 8 real-time clock ................................................... 8 watchdog timer .................................................. 9 timers ............................................................... 9 serial ports (sports) ............................................ 9 serial peripheral interface (spi) port ......................... 9 uart port ........................................................ 10 programmable flags (pfx) .................................... 10 parallel peripheral interface ................................... 10 dynamic power management ................................ 11 voltage regulation .............................................. 12 clock signals ..................................................... 12 booting modes ................................................... 13 instruction set description ................................... 14 development tools ............................................. 14 designing an emulator compatible processor board ... 15 pin descriptions .................................................... 16 specifications ........................................................ 19 recommended operating conditions ...................... 19 electrical characteristics ....................................... 19 absolute maximum ratings .................................. 20 esd sensitivity ................................................... 20 timing specifications ........................................... 21 clock and reset timing ..................................... 22 asynchronous memory read cycle timing ............ 23 asynchronous memory write cycle timing ........... 24 sdram interface timing .................................. 25 external port bus request and grant cycle timing .. 26 parallel peripheral interface timing ...................... 27 serial ports ..................................................... 28 serial peripheral interface (spi) port ?master timing ........................................... 33 serial peripheral interface (spi) port ?slave timing ............................................. 34 universal asynchronous receiver-transmitter (uart) port?receive and transmit timing ...... 35 programmable flags cycle timing ....................... 36 timer cycle timing .......................................... 37 jtag test and emulation port timing ................. 38 output drive currents ......................................... 39 power dissipation ............................................... 41 test conditions .................................................. 42 environmental conditions .................................... 45 160-lead bga pinout ............................................. 46 169-ball pbga pinout ............................................. 49 176-lead lqfp pinout ... ......................................... 51 outline dimensions ................................................ 53 ordering guide ..................................................... 56 revision history revision 0: initial version
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 3 of 56 | march 2004 general description the adsp-bf531/2/3 processors are members of the blackfin family of products, incorporating the analog devices/intel micro signal architecture (msa). blackfin processors combine a dual-mac state-of-the-art signal processing engine, the advantages of a clean, orthog onal risc-like microprocessor instruction set, and single-instruction, multiple-data (simd) multimedia capabilities into a single instruction-set architecture. the adsp-bf531/2/3 processors are completely code and pin compatible, differing only with respect to their performance and on-chip memory. specific perf ormance and memory configura- tions are shown in table 1 . by integrating a rich set of indu stry-leading system peripherals and memory, blackfin processors are the platform of choice for next-generation applications that require risc-like program- mability, multimedia support , and leading- edge signal processing in one integrated package. portable low power architecture blackfin processors provide world-class power management and performance. blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management, the ability to vary both the volt- age and frequency of operation to significantly lower overall power consumption. varying the voltage and frequency can result in a substantial reduction in power consumption, com- pared with just varying the frequency of operation. this translates into longer battery life for portable appliances. system integration the adsp-bf531/2/3 processors are highly integrated system- on-a-chip solutions for the next generation of digital communi- cation and consumer multimedia applications. by combining industry-standard interfaces with a high performance signal processing core, users can d evelop cost-effective solutions quickly without the need for costly external components. the system peripherals include a uart port, an spi port, two serial ports (sports), four general-purpose timers (three with pwm capability), a real-time clock, a watchdog timer, and a parallel peripheral interface. adsp-bf531/2/3 processor peripherals the adsp-bf531/2/3 processor cont ains a rich set of peripher- als connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see th e functional block diagram in figure 1 on page 1 ). the general-purpose peripherals include functions such as uart, time rs with pwm (pulse-width modulation) and pulse measurement capability, general-pur- pose flag i/o pins, a real-time clock, and a watchdog timer. this set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capa- bilities of the part . in addition to these general-purpose peripherals, the adsp-bf531/2/3 processor contains high speed serial and parallel ports for inte rfacing to a variety of audio, video, and modem codec functions an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources and power management control functions to tailor the performance and power characteristics of the pro- cessor and system to many application scenarios. all of the peripherals, except for general-purpose i/o, real- time clock, and timers, are suppo rted by a flexible dma struc- ture. there is also a separate memory dma channel dedicated to data transfers between th e processors various memory spaces, including external sdram and asynchronous memory. multiple on-chip buses runnin g at up to 133 mhz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. the adsp-bf531/2/3 processor in cludes an on-chip voltage regulator in support of th e adsp-bf531/2/3 processor dynamic power management capability. the voltage regulator provides a range of core voltag e levels from a single 2.25 v to 3.6 v input. the voltage regulator can be bypassed at the users discretion. blackfin processor core as shown in figure 2 on page 5 , the blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, an d a 40-bit shifter. the compu- tation units process 8-bit, 16-bit, or 32-bit data from the register file. the compute register file contai ns eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the result s into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, table 1. processor comparison adsp-bf531 adsp-bf532 adsp-bf533 maximum performance 400 mhz 800 mmacs 400 mhz 800 mmacs 600 mhz 1200 mmacs instruction sram/cache 16k bytes 16k bytes 16k bytes instruction sram 16k bytes 32k bytes 64k bytes data sram/cache 16k bytes 32k bytes 32k bytes data sram 32k bytes scratchpad 4k bytes 4k bytes 4k bytes
rev. 0 | page 4 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 saturation and rounding, and sign/exponent detection. the set of video instructions includes byte alignment and packing oper- ations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compare/select and vector search instructions. for certain instructions, two 16-bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a co mpute register). by al so using the second alu, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequencer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is provided to support zero-over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a mo dified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram an d cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain system resource s, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and co re resources. the blackfin processo r instruction set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent compiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. memory architecture the adsp-bf531/2/3 processor vi ews memory as a single uni- fied 4g byte address space, using 32-bit addresses. all resources, including internal memory, external memory, and i/o control registers, occupy separate sect ions of this common address space. the memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or sram, and larger, lower cost and performance off-chip memory systems. see figure 3 on page 5 , figure 4 on page 5 , and figure 5 on page 6 . the l1 memory system is the primary highest performance memory available to the blackfin processor. the off-chip mem- ory system, accessed through the external bus interface unit (ebiu), provides expansion with sdram, flash memory, and sram, optionally accessing up to 132m bytes of physical memory. the memory dma controller prov ides high bandwidth data- movement capability. it can perf orm block transfers of code or data between the internal memory and the external memory spaces. internal (on-chip) memory the adsp-bf// processor ha s three blocks of on-chip memory providing high bandwidth access to the core the first is the l instruction memory consisting of up to bytes sram of which bytes can be configured as a four-way set-associativ e cache this memory is accessed at full processor speed the second on-chip memory block is the l data memory con- sisting of up to two banks of up to bytes each each memory bank is configurable offering both cache and sram functional- ity this memory block is a ccessed at full processor speed the third memory block is a byte scratchpad sram which runs at the same speed as the l memories but is only accessible as data sram and cannot be configured as cache memory external (off-chip) memory the external bus interface can be used with both asynchronous devices such as sram flash eeprom rom and i/o devices and synchronous devices such as sdrams the bus width is always bits a is the least significant address of a -bit word -bit peripherals sh ould be addressed as if they were -bit devices where only th e lower bits of data should be used the pc-compliant sdram cont roller can be programmed to interface to up to m bytes of sdram the sdram con- troller allows one row to be open for each internal sdram bank for up to four internal sdram banks improving overall system performance
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 5 of 56 | march 2004 figure 2. blackfin processor core sp sequencer align decode loop buf fer dag0 da g 1 16 16 8 8 8 8 40 40 a0 a1 barrel shifter data arithmetic unit control un it address arithmetic unit fp p5 p4 p3 p2 p1 p0 i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 ld032bits ld132bits sd 3 2 bi ts r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l r7 .h r6 .h r5 .h r4 .h r3 .h r2 .h r1 .h r0 .h r7 r6 r5 r4 r3 r2 r1 r0 figure 3. adsp-bf533 inte rnal/external memory map reserved core mmr registers (2m byte) reserved scratchpad sram (4k byte) instruction sram (64k byte) system mmr registers (2m byte) reserved reserved data bank b sram / cache (16k byte) data bank b sram (16k byte) data bank a sram / cache (16k byte) async memory bank 3 (1m byte) async memory bank 2 (1m byte) async memory bank 1 (1m byte) async memory bank 0 (1m byte) sdram memory (16m byte to 128m byte) instruction sram / cache (16k byte) i n t e r n a l m e m o r y m a p e x t e r n a l m e m o r y m a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0xef00 0000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0x0800 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 reserved reserved data bank a sram (16k byte) 0xff90 0000 0xff80 0000 reserved figure 4. adsp-bf532 internal/external memory map core mmr registers (2m byte) reserved scratchpad sram (4k byte) system mmr registers (2m byte) reserved reserved data bank b sram / cache (16k byte) reserved data bank a sram / cache (16k byte) async memory bank 3 (1m byte) async memory bank 2 (1m byte) async memory bank 1 (1m byte) async memory bank 0 (1m byte) sdram memory (16m byte to 128m byte) instruction sram / cache (16k byte) i n t e r n a l m e m o r y m a p e x t e r n a l m e m o r y m a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa0 8000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0xef00 0000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0x0800 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 reserved reserved reserved 0xffa1 0000 instruction sram (32k byte) reserved
rev. 0 | page 6 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 the asynchronous memory cont roller can be programmed to control up to four banks of devi ces with very flexible timing parameters for a wide variety of devices. each bank occupies a 1m byte segment regardless of the size of the devices used, so that these banks will only be contiguous if each is fully popu- lated with 1m byte of memory. i/o memory space blackfin processors do not defi ne a separate i/o space all resources are mapped through th e flat -bit address space on-chip i/o devices have their control registers mapped into memory-mapped registers (mmrs) at addresses near the top of the g byte address space these are separated into two smaller blocks one of which contains the control mmrs for all core functions and the other of whic h contains the registers needed for setup and control of the on-c hip peripherals outside of the core the mmrs are accessible only in supervisor mode and appear as reserved spac e to on-chip peripherals booting the adsp-bf// processor co ntains a small boot kernel which configures the appropriate peripheral for booting if the adsp-bf// processor is conf igured to boot from boot rom memory space the processor starts executing from the on-chip boot rom for more information see booting modes on page event handling the event controller on the adsp-bf// processor handles all asynchronous and synchronous events to the processor the adsp-bf// processor provid es event handling that sup- ports both nesting and prioritiation esting allows multiple event service routines to be active simultaneously prioritiation ensures that servicing of a high er priority event takes prece- dence over servicing of a lower priority event the controller provides support for five different types of events emulation an emulation even t causes the processor to enter emulation mode allowing command and control of the processor via the jtag interface reset this event resets the processor on-maskable interrupt (mi) the mi event can be generated by the software watchdog timer or by the mi input signal to the processor the mi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system exceptions events that occur synchronously to program flow (ie the exception will be taken before the instruction is allowed to complete) conditions such as data alignment violations and undefined instructions cause exceptions interrupts events that occur asynchronously to program flow they are caused by in put pins timers and other peripherals as well as by an explicit software instruction each event type has an associated register to hold the return address and an associ ated return-from-event instruction when an event is triggered the state of the processor is saved on the supervisor stack the adsp-bf// processor e vent controller consists of two stages the core event cont roller (cec) and the system interrupt controller (sic) the core event controller works with the system interrupt controller to prioritie and control all system events conceptually in terrupts from the peripherals enter into the sic and are then routed directly into the general- purpose interrupts of the cec core event controller (cec) the cec supports nine general- purpose interrupts (ig) in addition to the dedicated interrupt and exception events of these general-purpose interrupts the two lowest-priority inter- rupts (ig) are recommended to be reserved for software interrupt handlers leaving seven prioritied interrupt inputs to support the peripherals of th e adsp-bf// processor table describes the inputs to the cec identifies their names in the event ector table (et ) and lists their priorities system interrupt controller (sic) the system interrupt contro ller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritied general-purpose interrupt inputs of the cec although the adsp-bf// processor provides a default mapping the user can alter the mappings and priorities of figure adsp-bf inte rnal/external memory map core mmr registers (m bte) resered scratchpad sram ( bte) sstem mmr registers (m bte) resered resered resered data ba a sram / cache ( bte) asc memor ba (m bte) asc memor ba (m bte) asc memor ba (m bte) asc memor ba (m bte) sdram memor (m bte to m bte) istructio sram / cache ( bte) i t e r a l m e m o r m a p e t e r a l m e m o r m a p xffff ffff xffe xffb xffa xffa xff xff xff xff xef x x x x x x x xffc xffb xffa resered resered resered xffa istructio sram ( bte) resered resered xffa c resered
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 7 of 56 | march 2004 interrupt events by writing the a ppropriate values into the inter- rupt assignment registers (iar). table 3 describes the inputs into the sic and the default mappings into the cec. event control the adsp-bf// processor provides the user with a very flexible mechanism to control th e processing of events in the cec three registers are used to coordinate and control events each register is bits wide cec interrupt latch register (ilat) the ilat register indicates when events have been latched the appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system this register is updated automatically by the controller but it may be written only when its corresponding imas bit is cleared cec interrupt mask regist er (imas) the imas reg- ister controls the masking and unmasking of individual events when a bit is set in the imas register that event is unmasked and will be processe d by the cec when asserted a cleared bit in the imas re gister masks the event pre- venting the processor from serv icing the event even though the event may be latched in the ilat register this register may be read or written while in supervisor mode (ote that general-purpose interrupts can be globally enabled and disabled with the sti and cli instructions respectively) cec interrupt pending regi ster (iped) the iped register keeps track of all nested events a set bit in the iped register indicates the event is currently active or nested at some level this regi ster is updated automatically by the controller but may be read while in supervisor mode the sic allows further control of event processing by providing three -bit interrupt control and st atus registers each register contains a bit corresponding to each of the peripheral interrupt events shown in table on page sic interrupt mask register (sicimas) this register controls the masking and unmasking of each peripheral interrupt event when a bit is set in the register that peripheral event is unmasked and will be processed by the system when asserted a cleare d bit in the register masks the peripheral event preventing the processor from servic- ing the event sic interrupt status regist er (sicisr) as multiple peripherals can be mapped to a single event this register allows the software to dete rmine which peripheral event source triggered the interrupt a set bit indicates the peripheral is asserting the interrupt and a cleared bit indi- cates the peripheral is not asserting the event sic interrupt wakeup enable register (siciwr) by enabling the corresponding bit in this register a peripheral can be configured to wake up the processor should the core be idled when the event is generated ( for more infor- mation see dynamic power management on page ) table 2. core event controller (cec) priority (0 is ighest) event class et entry 0 emulation/test control emu 1 reset rst 2non-maskable interruptnmi 3exceptionevx 4 reserved 5 hardware error ivhw 6core timerivtmr 7 general interrupt 7 ivg7 8 general interrupt 8 ivg8 9 general interrupt 9 ivg9 10 general interrupt 10 ivg10 11 general interrupt 11 ivg11 12 general interrupt 12 ivg12 13 general interrupt 13 ivg13 14 general interrupt 14 ivg14 15 general interrupt 15 ivg15 table 3. system interrupt controller (sic) peripheral interrupt event default mapping pll wakeup ivg7 dma error ivg7 ppi error ivg7 sport 0 error ivg7 sport 1 error ivg7 spi error ivg7 uart error ivg7 real-time clock ivg8 dma channel 0 (ppi) ivg8 dma channel 1 (sport 0 rx) ivg9 dma channel 2 (sport 0 tx) ivg9 dma channel 3 (sport 1 rx) ivg9 dma channel 4 (sport 1 tx) ivg9 dma channel 5 (spi) ivg10 dma channel 6 (uart rx) ivg10 dma channel 7 (uart tx) ivg10 timer 0 ivg11 timer 1 ivg11 timer 2 ivg11 pf interrupt a ivg12 pf interrupt b ivg12 dma channels 8 and 9 (memory dma stream 1) ivg13 dma channels 10 and 11 (memory dma stream 0) ivg13 software watchdog timer ivg13
rev. 0 | page 8 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 because multiple interrupt source s can map to a single general- purpose interrupt, multiple pulse assertions can occur simulta- neously, before or during interr upt processing for an interrupt event already detected on this interrupt input. the ipend reg- ister contents are monitored by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected (detection requ ires two core clock cycles). the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec will recognize and queue the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the general- purpose interrupt to the ipend output asserted is three core clock cycles; however, the latenc y can be much higher, depend- ing on the activity within and the state of the processor. dma controllers the adsp-bf531/2/3 processor has multiple, independent dma controllers that support au tomated data transfers with minimal overhead for the proc essor core. dma transfers can occur between the adsp-bf531/2/3 processor's internal memo- ries and any of its dma-capabl e peripherals. additionally, dma transfers can be accomplished between any of the dma- capable peripherals and external devices connected to the exter- nal memory interfaces, including the sdram controller and the asynchronous memory cont roller. dma-capable peripher- als include the sports, spi port, uart, and ppi. each individual dma-capable peripher al has at least one dedicated dma channel. the adsp-bf531/2/3 processor dma controller supports both 1-dimensional (1d) and 2-dimensional (2d) dma transfers. dma transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. the 2d dma capability support s arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 3 2k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved data streams. this feature is especially useful in video applications where data can be de-interleaved on the fly. examples of dma types supported by the adsp-bf531/2/3 processor dma controller include: ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing bu ffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a linked list of descriptors ? 2-d dma using an array of descriptors, specifying only the base dma address wi thin a common page in addition to the dedicated peripheral dma channels, there are two memory dma channels provided for transfers between the various memories of the adsp -bf531/2/3 processor system. this enables transfers of blocks of data betw een any of the memories?including external sdram, rom, sram, and flash memory?with minimal proc essor intervention. memory dma transfers can be controlled by a very flexible descriptor based methodology or by a standa rd register based autobuffer mechanism. real-time clock the adsp-bf531/2/3 processor real-time clock (rtc) pro- vides a robust set of digital watch features, including current time, stopwatch, and alarm. the rtc is clocked by a 32.768 khz crystal external to the adsp-bf531/2/3 processor. the rtc peripheral has dedicated power supply pins so that it can remain powered up and cloc ked even when the rest of the processor is in a low-power st ate. the rtc provides several programmable interrupt options, including interrupt per sec- ond, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a pro- grammed alarm time. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and a 32,768-day counter. when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. there are two alarms: the first alarm is for a time of day. the second alarm is for a day and time of that day. the stopwatch function counts down from a programmed value, with one-second resolution. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like other peripherals, the rtc can wake up the processor from sleep mode upon generation of any rtc wakeup event. additionally, an rtc wakeup even t can wake up the processor from deep sleep mode, and wake up the on-chip internal volt- age regulator from a powered-down state. connect rtc pins rtxi and rtxo with external components as shown in figure 6 . figure 6. external components for rtc rtxo c1 c2 x1 suggested components: ecliptek ec38j (through-hole package) epson mc405 12 pf load (surface-mount package) c1 = 22 pf c2 = 22 pf r1 = 10 m ohm note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3 pf. rtxi r1
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 9 of 56 | march 2004 watchdog timer the adsp-bf531/2/3 processor incl udes a 32-bit timer that can be used to implement a software watchdog function. a software watchdog can improve system avai lability by forcing the proces- sor to a known state through gene ration of a hardware reset, non-maskable interrupt (nmi), or general-purpose interrupt, if the timer expires before being reset by software. the program- mer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the programmed value. this prot ects the system from remain- ing in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to generate a hardware reset, the watchdog timer resets both the core and the adsp-bf531/2/3 processor periph- erals. after a reset, software ca n determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the syst em clock (sclk), at a maximum frequency of f sclk . timers there are four general-purpose programmable timer units in the adsp-bf531/2/3 processor. th ree timers have an external pin that can be configured eith er as a pulse-width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse-widths and periods of external events. these timers can be synchr onized to an external clock input to the pf1 pin, an external clock input to the ppi_clk pin, or to the internal sclk. the timer units can be used in conjunction with the uart to measure the width of the pulses in the data stream to provide an auto-baud detect function for a serial channel. the timers can generate interrupts to the processor core provid- ing periodic events for synchronization, either to the system clock or to a count of external signals. in addition to the three general-purpose programmable timers, a fourth timer is also provided. this extra timer is clocked by the internal processor clock and is ty pically used as a system tick clock for generation of operating system periodic interrupts. serial ports (sports) the adsp-bf531/2/3 processor in corporates two dual-channel synchronous serial ports (sport 0 and sport1) for serial and multiprocessor communications. the sports support the fol- lowing features: i 2 s capable operation. bidirectional operation C each sport has two sets of inde- pendent transmit and receive pi ns, enabling eight channels of i 2 s stereo audio. buffered (8-deep) transmit and receive ports C each port has a data register for transfe rring data words to and from other processor components and shift registers for shifting data in and out of the data registers. clocking C each transmit and re ceive port can either use an external serial clock or generate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. word length C each sport su pports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first. framing C each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. companding in hardware C each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. dma operations with single-cycle overhead C each sport can automatically receive and tr ansmit multiple buffers of memory data. the processor can link or chain sequences of dma transfers between a sport and memory. interrupts C each transmit and receive port generates an interrupt upon completing the transfer of a data-word or after transferring an entire da ta buffer or buffers through dma. multichannel capability C each sport supports 128 chan- nels out of a 1024-channel wind ow and is compatible with the h.100, h.110, mvip-90, and hmvip standards. serial peripheral interface (spi) port the adsp-bf531/2/3 processor ha s an spi-compatible port that enables the processor to communicate with multiple spi- compatible devices. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosi, and master input- slave output, miso) and a clock pin (serial clock, sck). an spi chip select input pin (spiss ) lets other spi devices select the processor, and seven spi chip select output pins (spisel7C1 ) let the processor select other spi devices. the spi select pins are reconfigured programmable flag pins. using these pins, the spi port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. the spi ports baud rate and clock phase/ polarities are pro- grammable, and it has an integrated dma controller, configurable to support transmit or receive data streams. the spis dma controller can only serv ice unidirectional accesses at any given time. the spi ports clock rate is calculated as: where the 16-bit spi_baud register contains a value of 2 to 65,535. spi clock rate f sclk 2 spi_baud -------------------------------- - =
rev. 0 | page 10 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. the serial clock line sy nchronizes the shifting and sam- pling of data on the two serial data lines. uart port the adsp-bf531/2/3 processor provides a full-duplex univer- sal asynchronous receiver/transmitter (uart) port, which is fully compatible with pc-standard uarts. the uart port provides a simplified uart inte rface to other peripherals or hosts, supporting full-duplex, dma-supported, asynchronous transfers of serial data. the uart port includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. the uart port supports two modes of operation: ? pio (programmed i/o) ? the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) ? the dma controller transfers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. the uart port's baud rate, serial data fo rmat, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk / 1,048,576) to (f sclk /16) bits per second. ? supporting data formats fr om 7 to12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. the uart port?s clock ra te is calculated as: where the 16-bit uart_divisor comes from the dlh register (most significant 8 bits) and d ll register (least significant 8bits). in conjunction with the general-purpose timer functions, auto- baud detection is supported. the capabilities of th e uart are further extended with support for the infrared data association (irda ? ) serial infrared physi- cal layer link specification (sir) protocol. programmable flags (pfx) the adsp-bf531/2/3 processor ha s 16 bidirectional, general- purpose programmable flag (pf15?0) pins. each programma- ble flag can be individually controlled by manipulation of the flag control, status and interrupt registers: ? flag direction control register ? specifies the direction of each individual pfx pin as input or output. ? flag control and status re gisters ? the adsp-bf531/2/3 processor employs a ?write one to modify? mechanism that allows any combination of individual flags to be modified in a single instruction, with out affecting the level of any other flags. four control regi sters are provided. one regis- ter is written in order to set flag values, one register is written in order to clear flag values, one register is written in order to toggle flag values, and one register is written in order to specify a flag value. reading the flag status register allows software to interrogate the sense of the flags. ? flag interrupt mask register s ? the two flag interrupt mask registers allow each individual pfx pin to function as an interrupt to the processor. similar to the two flag con- trol registers that are used to set and clear individual flag values, one flag interrupt mask register sets bits to enable interrupt function, and the other flag interrupt mask reg- ister clears bits to disable interrupt function. pfx pins defined as inputs can be configured to generate hardware interrupts, while output pfx pins can be triggered by soft- ware interrupts. ? flag interrupt sensitivity registers ? the two flag inter- rupt sensitivity registers specify whether individual pfx pins are level- or edge-sensi tive and specify? if edge-sensi- tive?whether just the rising ed ge or both the rising and falling edges of the signal ar e significant. one register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity. parallel peripheral interface the processor provides a parallel peripheral interface (ppi) that can connect directly to parallel a/d and d/a converters, itu-r 601/656 video encoders and deco ders, and other general-pur- pose peripherals. the ppi consis ts of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. the input clock supports parallel data rates up to half the system clock rate. in itu-r 656 modes, the ppi recei ves and parses a data stream of 8-bit or 10-bit data elements . on-chip decode of embedded preamble control and synchronization information is supported. three distinct itu-r 656 modes are supported: ? active video only - the ppi do es not read in any data between the end of active video (eav) and start of active video (sav) preamble symbols, or any data present during uart clock rate f sclk 16 uart_divisor ----------------------------------------------- - =
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 11 of 56 | march 2004 the vertical blanking intervals. in this mode, the control byte sequences are not stored to memory they are filtered by the ppi. vertical blanking only - th e ppi only transfers vertical blanking interval (vbi) data, as well as horizontal blanking information and control byte sequences on vbi lines. entire field - the entire inco ming bitstream is read in through the ppi. this includes active video, control pream- ble sequences, and ancillary da ta that may be embedded in horizontal and vertical blanking intervals. though not explicitly supporte d, itu-r 656 output functional- ity can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and stre aming the data out the ppi in a frame sync-less mode. the processors 2d dma feat ures facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. the general-purpose modes of th e ppi are intended to suit a wide variety of data capture an d transmission applications. the modes are divided into four main categories, each allowing up to 16 bits of data transfer per ppi_clk cycle: data receive with internally generated frame syncs data receive with externally generated frame syncs data transmit with internally generated frame syncs data transmit with externally generated frame syncs these modes support adc/dac conn ections, as well as video communication with hardware signaling. many of the modes support more than one level of frame synchronization. if desired, a programmable delay can be inserted between asser- tion of a frame sync and reception/transmission of data. dynamic power management the adsp-bf531/2/3 processor prov ides five operating modes, each with a different performanc e/power profile. in addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. control of clocking to each of the adsp-bf531/2/3 processor periph erals also reduces power con- sumption. see table 4 for a summary of the power settings for each mode. full-on operating modemaximum performance in the full-on mode the pll is enabled and is not bypassed providing capability for maximum operational frequency this is the power-up default execution state in which maximum per- formance can be achieved the processor core and all enabled peripherals run at full speed active operating modemoderate power savings in the active mode the pll is enabled but bypassed because the pll is bypassed the processo rs core clock (ccl) and sys- tem clock (scl) run at the input clock (cli) frequency in this mode the cli to ccl multiplier ratio can be changed although the changes are not realied until the full-on mode is entered dma access is available to appropriately configured l memories in the active mode it is possible to disable the pll through the pll control register (pllctl) if disabled the pll must be re-enabled before transitioning to the full-on or sleep modes hibernate operating mode maximum static power savings the hibernate mode maximies static power savings by dis- abling the voltage and clocks to the processor core (ccl) and to all the synchronous peripher als (scl) the internal voltage regulator for the processor can be shut off by writing b to the fre bits of the rctl regi ster this disables both ccl and scl furthermore it sets the internal power supply volt- age ( ddit ) to to provide the lowest static power dissipation any critical information stored internally (memory contents register contents etc) must be written to a non-vola- tile storage device prior to remo ving power if the processor state is to be preserved since ddet is still supplied in this mode all of the external pins tri-state unless otherwise specified this allows other devices that may be connected to the processor to have power still applied without drawing unwanted current the internal supply regulator can be woken up either by a real- time clock wakeup or by asserting the reset pin sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by dis- abling the clock to the proce ssor core (ccl) the pll and system clock (scl) however continue to operate in this mode typically an external event or rtc activity will wake up the processor when in the slee p mode assertion of wakeup will cause the processor to sense the value of the bpass bit in the pll control register (pllctl) if bpass is disabled the processor will transition to th e full on mode if bpass is enabled the processor will transition to the active mode when in the sleep mode system dma access to l memory is not supported deep sleep operating modemaximum dynamic power savings the deep sleep mode maximie s dynamic power savings by disabling the clocks to the proce ssor core (ccl) and to all syn- chronous peripherals (scl) as ynchronous peripherals such table 4. power settings mode pll pll bypassed core clock (cclk) system clock (sclk) core power full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled disabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off
rev. 0 | page 12 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 as the rtc, may still be running but will not be able to access internal resources or external memory. this powered-down mode can only be exited by assertion of the reset interrupt (reset ) or by an asynchronous interrupt generated by the rtc. when in deep sleep mode , an rtc asynchronous inter- rupt causes the processor to tr ansition to the active mode. assertion of reset while in deep sleep mode causes the pro- cessor to transition to the full-on mode. power savings as shown in table the adsp-bf// processor supports three different power domains the use of multiple power domains maximies flexibility while maintaining compliance with industry standards and conventions by isolating the inter- nal logic of the adsp-bf// processor into its own power domain separate from the rtc and other i/o the processor can take advantage of dynamic power management without affecting the rtc or other i/o d evices there are no sequencing requirements for the various power domains the power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage for example reducing the clock frequency by results in a reduction in dynamic power dissipation while reducing the voltage by re duces dynamic power dissipation by more than further thes e power savings are additive in that if the clock frequency and supply voltage are both reduced the power savings can be dramatic the dynamic power management feature of the adsp- bf// processor allows both the processors input voltage ( ddit ) and clock frequency (f ccl ) to be dynamically controlled the savings in power dissipation can be modeled using the power savings factor and p ower savings calculations the power savings factor is calculated as where the variables in the equations are f cclom is the nominal core clock frequency f cclred is the reduced core clock frequency dditom is the nominal internal supply voltage dditred is the reduced internal supply voltage t om is the duration running at f cclom t red is the duration running at f cclred the percent power savings is calculated as oltage regulatio the blackfin processor provides an on-chip voltage regulator that can generate processor core voltage levels (- / ) to (- / ) from an external to supply figure shows the typical external components required to complete the power management system the regu- lator controls the internal logic voltage levels and is programmable with the oltag e regulator control register (rctl) in increments of m to reduce standby power consumption the internal voltage regulator can be programmed to remove power to the processor core while keeping i/o power ( ddet ) supplied while in hibernation ddet can still be applied eliminating the need for external buffers the voltage regulator can be activated from this power-down state either through an rtc wakeup or by asserting reset which will then initiate a boot sequence the regulator can also be disabled and bypassed at the users discretion cloc sigals the adsp-bf// processor can be clocked by an external crystal a sine wave input or a buffered shaped clock derived from an external clock oscillator if an external clock is used it should be a ttl compatible signal and must not be halted changed or operated below the speci- fied frequency during normal operation this signal is connected to the processors cl i pin when an external clock is used the tal pin must be left unconnected table 5. power domains power domain dd range all internal logic, except rtc v ddint rtc internal logic and crystal i/o v ddrtc all other i/o v ddext power savings factor f cclkred f cclknom --------------------- v ddintred v ddintnom -------------------------- ?? ?? 2 t red t nom ------------ - ? ? ? ? = * see ee-228: switching regulator desi gn considerations for adsp-bf533 blackfin processors. figure 7. voltage regulator circuit % power savings 1 power savings factor ? () 100% = v ddext v ddint vr out 1-0 external components 2.25v to 3.6v input voltage range nds8434 zhcs1000 100 f 1f 10 h 0.1 f note: vr out 1-0shouldbetiedtogetherexternally and designer should minimize trace length to nds8434. 100 f
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 13 of 56 | march 2004 alternatively, because the adsp -bf531/2/3 processor includes an on-chip oscillator circuit, an external crystal may be used. the crystal should be connecte d across the clkin and xtal pins, with two capacitors connected as shown in figure 8 . capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. a parallel-resonant, fundamental frequency, micropro cessor-grade crystal should be used. as shown in figure 9 on page 13 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a user prog rammable 1x to 63x multiplica- tion factor (bounded by specified minimum and maximum vco frequencies). the default multiplier is 10x, but it can be modified by a software instru ction sequence. on-the-fly fre- quency changes can be effected by simply writing to the pll_div register. all on-chip peripherals are clocke d by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 6 illustrates typical system clock ratios. the maximum frequency of the system clock is f sclk . note that the divisor ratio must be chosen to limit the system clock fre- quency to its maximum of f sclk . the ssel value can be changed dynamically without any pll lo ck latencies by writing the appropriate values to the pll divisor register (pll_div). the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 7 . this programmable core cloc k capability is useful for fast core frequency modifications. booting modes the adsp-bf531/2/3 processor ha s two mechanisms (listed in table 8 ) for automatically loading internal l1 instruction mem- ory after a reset. a third mode is provided to execute from external memory, bypassi ng the boot sequence. figure 8. external crystal connections figure 9. frequency modification methods clkin clkout xtal pll 0. 5 table 6. example system clock ratios signal name ssel30 divider ratio co/sclk example frequency ratios (m) co sclk 0001 1:1 100 100 0011 3:1 400 133 1010 10:1 500 50 table 7. core clock ratios signal name csel10 divider ratio co/cclk example frequency ratios co cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25 table 8. booting modes bmode10 description 00 execute from 16-bit external memory (bypass boot rom) 01 boot from 8-bit or 16-bit flash 10 reserved 11 boot from spi serial eeprom (8-, 16-, or 24-bit address range)
rev. 0 | page 14 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 the bmode pins of the reset configuration register, sampled during power-on resets and so ftware-initiated resets, imple- ment the following modes: ? execute from 16-bit external memory ? execution starts from address 0x2000 0000 with 16-bit packing. the boot rom is bypassed in this mode. all configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle r/w access time s; 4-cycle setup). ? boot from 8-bit or 16-bit ex ternal flash memory ? the flash boot routine located in boot rom memory space is set up using asynchronous me mory bank 0. all configura- tion settings are set for the slowest device possible (3-cycle hold time; 15-cycl e r/w access times; 4-cycle setup). ? boot from spi serial eeprom (8, 16, or 24-bit addressable) ? the spi uses the pf2 output pin to select a single spi eeprom device, submits successive read com- mands at addresses 0x00, 0x0000, and 0x000000 until a valid 8, 16, or 24-bit addre ssable eeprom is detected, and begins clocking data into the beginning of l1 instruction memory. for each of the boot modes, an 10-byte header is first read from an external memory device. the header specifies the number of bytes to be transferred and th e memory destination address. multiple memory blocks may be loaded by any boot sequence. once all blocks are loaded, pr ogram execution commences from the start of l1 instruction sram. in addition, bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. for this case, the processor jumps directly to the beginning of l1 instruction memory. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax desi gned for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. the instruction set also provides fully featured multifunction instructions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/application code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core processor resources. the assembly language, which ta kes advantage of the proces- sor?s unique architecture, offers the following advantages: ? seamlessly integrated dsp/cpu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, which include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools the adsp-bf531/2/3 processor is supported with a complete set of crosscore ? ? software and hardware development tools, including analog devi ces emulators and visualdsp++ ? ? development environment. the sa me emulator hardware that supports other blackfin processo rs also fully emulates the adsp-bf531/2/3 processor. the visualdsp++ project manage ment environment lets pro- grammers develop and debug an application. this environment includes an easy to use assemble r (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instru ction-level simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathematical functions. a key point for these tools is c/c++ code efficiency. the compiler ha s been develope d for efficient translation of c/c++ code to processor a ssembly. the processor has architectural features that improve the efficiency of com- piled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designer?s development schedule , increasing pr oductivity. sta- tistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and effi- ciently. by using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and as sembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information). ? insert breakpoints. ? crosscore is a registered trademark of analog devices, inc. ? visualdsp++ is a registered trademark of analog devices, inc.
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 15 of 56 | march 2004 set conditional breakpoints on registers, memory, and stacks. trace instruction execution. perform linear or statistical profiling of program execution. fill, dump, and graphically pl ot the contents of memory. perform source level debugging. create custom debugger windows. the visualdsp++ idde lets pr ogrammers define and manage software development. its dialog boxes and property pages let programmers configure and manage all of the blackfin develop- ment tools, including the color syntax highlighting in the visualdsp++ editor. this capabi lity permits programmers to: control how the development tools process inputs and generate outputs. maintain a one-to-one corres pondence with the tools command line switches. the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored specifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unsche duled regions, semaphores, events, and device flags. the vd k also supports priority-based, preemptive, cooperative, an d time-sliced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but ca n also be used via standard command line tools. when the vdk is used, the development environment assists the develope r with many error-prone tasks and assists in managing system resources, automating the gen- eration of various vdk based objects, and visualizing the system state, when debugging an application that uses the vdk. vcse is analog devices techno logy for creati ng, using, and reusing software components (independent modules of sub- stantial functionality) to quickly and reliably assemble software applications. download components from the web and drop them into the application. publish component archives from within visualdsp++. vcse su pports component implementa- tion in c/c++ or assembly language. use the expert linker to visua lly manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical form, easily move code and data to different area s of the processor or external memory with the drag of the mouse, examine run time stack and heap usage. the expert linker is fully compatible with existing linker definition file (ldf), allowing the develop er to move between the graphi- cal and textual environments. analog devices emulators us e the ieee 1149.1 jtag test access port of the adsp-bf531/2 /3 processor to monitor and control the target board proce ssor during emulation. the emu- lator provides full speed emulation, allowing inspection and modification of memory, regist ers, and processor stacks. non- intrusive in-circuit emulation is assured by the use of the processors jtag interfacethe emulator does not affect target system loadin g or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the bl ackfin processor family. hard- ware tools include blackfin proc essor pc plug-in cards. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator compatible processor board the analog devices family of em ulators are tools that every sys- tem developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag processor. the emulator uses the tap to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the proces- sor must be halted to send da ta and commands, but once an operation has been completed by the emulator, the processor system is set running at full sp eed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the processors jtag port to the emulator. for details on target board design issues including mechanical layout, single processor conne ctions, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices we site wwwanalogcom use site search on ee-68 this document is udated regularl to kee ace with imrovem ents to emulator suort
rev. 0 | page 16 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 pin descriptions adsp-bf531/2/3 processor pin definitions are listed in table 9 . all pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins, which are driven high. if br is active, then the memory pi ns are also three-stated. all unused i/o pins have their input buffers disabled with the exception of the pins that need pullups or pulldowns as noted in the table footnotes. in order to maintain maximum functionality and reduce pack- age size and pin count, some pins have dual, multiplexed functionality. in cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate function- ality is shown in italics. table 9. pin descriptions pin name i/o function driver type 1 memory interface addr19C1 o address bus for async/sync access a 2 data15C0 i/o data bus for async/sync access a 2 abe1C0 /sdqm1C0 o byte enables/data masks for async/sync access a 2 br 3 ibus request bg obus grant a 2 bgh obus grant hang a 2 asynchronous memory control ams3C0 obank select a 2 ardy i hardware ready control aoe ooutput enable a 2 are oread enable a 2 awe owrite enable a 2 synchronous memory control sras o row address strobe a 2 scas o column address strobe a 2 swe owrite enable a 2 scke o clock enable a 2 clkout o clock output b 4 sa10 o a10 pin a 2 sms obank select a 2 timers tmr0 i/o timer 0 c 5 tmr1/ ppi_fs1 i/o timer 1/ ppi frame sync1 c 5 tmr2/ ppi_fs2 i/o timer 2/ ppi frame sync2 c 5
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 17 of 56 | march 2004 parallel peripheral interface port/gpio pf0/ spiss i/o programmable flag 0/ spi slave select input c 5 pf1 /spisel1/tmrclk i/o programmable flag 1/ spi slave select enable 1/external timer reference c 5 pf2/ spisel2 i/o programmable flag 2/ spi slave select enable 2 c 5 pf3/ spisel3/ppi_fs3 i/o programmable flag 3/ spi slave select enable 3/ppi frame sync 3 c 5 pf4/ spisel4/ppi15 i/o programmable flag 4/ spi slave select enable 4 / ppi 15 c 5 pf5/ spisel5/ppi14 i/o programmable flag 5/ spi slave select enable 5 / ppi 14 c 5 pf6/ spisel6/ppi13 i/o programmable flag 6/ spi slave select enable 6 / ppi 13 c 5 pf7/ spisel7/ppi12 i/o programmable flag 7/ spi slave select enable 7 / ppi 12 c 5 pf8/ ppi11 i/o programmable flag 8/ ppi 11 c 5 pf9/ ppi10 i/o programmable flag 9/ ppi 10 c 5 pf10/ ppi9 i/o programmable flag 10/ ppi 9 c 5 pf11/ ppi8 i/o programmable flag 11/ ppi 8 c 5 pf12/ ppi7 i/o programmable flag 12/ ppi 7 c 5 pf13/ ppi6 i/o programmable flag 13/ ppi 6 c 5 pf14/ ppi5 i/o programmable flag 14/ ppi 5 c 5 pf15/ ppi4 i/o programmable flag 15/ ppi 4 c 5 ppi3C0 i/o ppi3C0 c 5 ppi_clk i ppi clock c 5 serial ports rsclk0 i/o sport0 receive serial clock d 6 rfs0 i/o sport0 receive frame sync c 5 dr0pri i sport0 receive data primary dr0sec i sport0 receive data secondary tsclk0 i/o sport0 transmit serial clock d 6 tfs0 i/o sport0 transmit frame sync c 5 dt0pri o sport0 transmit data primary c 5 dt0sec o sport0 transmit data secondary c 5 rsclk1 i/o sport1 receive serial clock d 6 rfs1 i/o sport1 receive frame sync c 5 dr1pri i sport1 receive data primary dr1sec i sport1 receive data secondary tsclk1 i/o sport1 transmit serial clock d 6 tfs1 i/o sport1 transmit frame sync c 5 dt1pri o sport1 transmit data primary c 5 dt1sec o sport1 transmit data secondary c 5 spi port mosi i/o master out slave in c 5 miso 7 i/o master in slave out c 5 sck i/o spi clock d 6 table 9. pin descriptions (continued) pin name i/o function driver type 1
rev. 0 | page 18 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 uart port rx i uart receive tx o uart transmit c 5 real time clock rtxi 8 irtc crystal input rtxo o rtc crystal output jtag port tck i jtag clock tdo o jtag serial data out c 5 tdi i jtag serial data in tms i jtag mode select trst 9 i jtag reset emu o emulation output c 5 clock clkin i clock/crystal input xtal o crystal output mode controls reset i reset nmi 8 i non-maskable interrupt bmode1C0 i boot mode strap voltage regulator vrout1C0 o external fet drive supplies v ddext p i/o power supply v ddint p core power supply v ddrtc preal time clock power supply gnd g external ground 1 refer to figure 26 on page 39 to figure 30 on page 40 . 2 see figure 25 and figure 26 on page 39 3 this pin should be pulled high when not used. 4 see figure 27 and figure 28 on page 39 5 see figure 29 and figure 30 on page 40 6 see figure 31 and figure 32 on page 40 7 this pin should always be pulled high through a 4.7k ohm resistor if booting via the spi port. 8 this pin should always be pulled low when not used. 9 this pin should be pulled low if the jtag port will not be used. table 9. pin descriptions (continued) pin name i/o function driver type 1
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 19 of 56 | march 2004 specifications component specifications are subject to change without notice. recommended operating conditions electrical characteristics parameter minimum nominal maximum unit v ddint internal supply voltage 0.8 1.2 1.32 v v ddext external supply voltage 2.25 2.5 or 3.3 3.6 v v ddrtc real-time clock power supply voltage 2.25 3.6 v v ih high level input voltage 1, 2 @ v ddext =maximum 1 the adsp-bf531/2/3 processor is 3.3 v tolerant (always accepts up to 3.6 v maximum v ih ), but voltage compliance (on outputs, v oh ) depends on the input v ddext , because v oh (maximum) approximately equals v ddext (maximum). this 3.3 v tolerance applies to bidirectional pins (data15C0, tmr2C0, pf15C0, ppi3C0, rsclk1C0, tsclk1C0, rfs1C0, tfs1C0 , mosi, miso, sck) and input only pins (br , ardy, ppi_clk, dr0pri, dr0sec, dr1pri, dr1sec, rx, rtxi, tck, tdi, tms, trst , clkin, reset , nmi, and bmode1C0). 2 parameter value applies to all input and bidirectional pins except clkin. 2.0 3.6 v v ihclkin high level input voltage 3 @ v ddext =maximum 3 parameter value applie s to clkin pin only. 2.2 3.6 v v il low level input voltage 2, 4 @ v ddext =minimum 4 parameter value applies to all input and bidirectional pins. C0.3 0.6 v parameter test conditions minimum maximum unit v oh high level output voltage 1 1 applies to output and bidirectional pins. @ v ddext =3.0v, i oh = C0.5 ma 2.4 v v ol low level output voltage 2 @ v ddext =3.0v, i ol = 2.0 ma 0.4 v i ih high level input current 2 2 applies to input pins except jtag inputs. @ v ddext =maximum, v in = v dd maximum 10.0 a i ihp high level input current jtag 3 3 applies to jtag input pins (tck, tdi, tms, trst) . @ v ddext =maximum, v in = v dd maximum 20.0 a i il low level input current 4 @ v ddext =maximum, v in = 0 v 10.0 a i ozh three-state leakage current 4 4 applies to three-statable pins. @ v ddext = maximum, v in = v dd maximum 10.0 a i ozl three-state leakage current 5 @ v ddext = maximum, v in = 0 v 10.0 a c in input capacitance 5, 6 5 applies to all signal pins. 6 guaranteed, but not tested. f in = 1 mhz, t a mbient = 25c, v in = 2.5 v 8.0 pf
rev. 0 | page 20 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 absolute maximum ratings stresses greater than those listed in the table may cause perma- nent damage to the device. these are stress ratings only. functional operation of the devi ce at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for proper sdram controller operation, the maximum load capacitance is 50 pf (at 3.3 v) or 30 pf (at 2.5 v) for addr19?1, data15?0, abe1?0 /sdqm1?0, clkout, scke, sa10, sras , scas , swe , and sms . esd sensitivity parameter rating internal (core) supply voltage (v ddint )C0.3 v to +1.4 v external (i/o) supply voltage (v ddext )C0.3 v to +3.8 v input voltage C0.5 v to 3.6 v output voltage swing C0.5 v to v ddext +0.5 v load capacitance 200 pf adsp-bf533 core clock (cclk) 600 mhz adsp-bf532/bf531 core clock (cclk) 400 mhz peripheral clock (sclk) 133 mhz storage temperature range C65oc to +150oc junction temperature under bias 125oc caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-bf531/2/3 processor features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 21 of 56 | march 2004 timing specifications table 10 through table 14 describe the timing requirements for the adsp-bf531/2/3 processor cloc ks. take care in selecting msel, ssel, and csel ratios so as not to exceed the maximum core clock and system clock as described in absolute maximum ratings on page 20 , and the voltage controlled oscillator (vco) operating frequencies described in table 13 . table 13 describes phase-locked loop operating conditions. table 10. core and system cloc k requirementsadsp-bf533skbc600 parameter min max nit t cclk core cycle period (v ddint =1.2 vC5%) 1.67 ns t cclk core cycle period (v ddint =1.1 vC5%) 2.10 ns t cclk core cycle period (v ddint =1.0 vC5%) 2.35 ns t cclk core cycle period (v ddint =0.9 vC5%) 2.66 ns t cclk core cycle period (v ddint =0.8 v) 4.00 ns t sclk system clock period maximum of 7.5 or t cclk ns table 11. core and system clock requirem entsadsp-bf533sbbc500 and adsp-bf533sbbz500 parameter min max nit t cclk core cycle period (v ddint =1.2 vC5%) 2.0 ns t cclk core cycle period (v ddint =1.1 vC5%) 2.25 ns t cclk core cycle period (v ddint =1.0 vC5%) 2.50 ns t cclk core cycle period (v ddint =0.9 vC5%) 3.00 ns t cclk core cycle period (v ddint =0.8 v) 4.00 ns t sclk system clock period maximum of 7.5 or t cclk ns table 12. core and system clock requir ementsadsp-bf532/531 all package types parameter min max nit t cclk core cycle period (v ddint =1.2 vC5%) 2.5 ns t cclk core cycle period (v ddint =1.1 vC5%) 2.75 ns t cclk core cycle period (v ddint =1.0 vC5%) 3.00 ns t cclk core cycle period (v ddint =0.9 vC5%) 3.25 ns t cclk core cycle period (v ddint =0.8 v) 4.0 ns t sclk system clock period maximum of 7.5 or t cclk ns table 13. phase-locked loop operating conditions parameter min max nit f vco voltage controlled oscillator (vco) frequency 50 max cclk mhz table 14. maximum sclk conditions parameter condition ddet 3.3 ddet 2.5 nit mbga f sclk v ddint >= 1.14 v 133 133 mhz f sclk v ddint < 1.14 v 100 100 mhz lqfp f sclk v ddint >= 1.14 v 133 133 1 mhz f sclk v ddint < 1.14 v 83 83 1 mhz 1 set bit 7 (output delay) of pll_ctl register.
rev. 0 | page 22 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 clock and reset timing table and figure describe clock and reset operations per absolute maximum ratings on page combinations of cli and clock multipliers must not select core/peripheral clocks in excess of / mh table 15. clock and reset timing parameter min max nit timing requirements t ckin clkin period 25.0 100.0 ns t ckinl clkin low pulse 1 10.0 ns t ckinh clkin high pulse 1 10.0 ns t wrst reset asserted pulse width low 2 11 t ckin ns 1 applies to bypass mode and non-bypass mode. 2 applies after power-up sequence is complete . at power-up, the processors internal phase-locked loop requires no more than 2000 clkin cycles, while reset is asserted, assuming stable power supplies and clkin (not includ ing start-up time of external clock oscillator). figure 10. clock and reset timing reset cli cih cil wrst ci
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 23 of 56 | march 2004 asynchronous memory read cycle timing table 16. asynchronous memory read cycle timing parameter min max nit timing requirements t sdat data15C0 setup before clkout 2.1 ns t hdat data15C0 hold after clkout 0.8 ns t sardy ardy setup before clkout 4.0 ns t hardy ardy hold after clkout 0.0 ns switching characteristics t do output delay after clkout 1 1 output pins include ams3C0 , abe1C0 , addr19C1, aoe , are . 6.0 ns t ho output hold after clkout 1 0.8 ns figure 11. asynchronous memory read cycle timing t do t sdat clkout amsx abe1C0 ho be aress rea hat ata10 aoe o sar har access etee ccles hol 1ccle are har ar ar11 setp ccles programme rea access ccles ho sar
rev. 0 | page 24 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 asynchronous memory write cycle timing table 17. asynchronous memory write cycle timing parameter min max nit timing requirements t sardy ardy setup before clkout 4.0 ns t hardy ardy hold after clkout 0.0 ns switching characteristics t ddat data15 C0 disable after clkout 6.0 ns t endat data15C0 enable after clkout 1.0 ns t do output delay after clkout 1 1 output pins include ams3C0 , abe1C0 , addr19C1, data15C0, aoe, awe . 6.0 ns t ho output hold after clkout 1 0.8 ns figure 12. asynchronous memory write cycle timing t do t end at clkout amsx abe10 be, address t ho write data t ddat data150 awe t sardy t hardy setup 2cycles programmed write access 2 cycles access extended 1cycle hold 1cycle ardy addr191 t ho t sardy t do
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 25 of 56 | march 2004 sdram interface timing table 18. sdram interface timing 1 1 for ddint 1.2 . parameter min max nit timing requirements t ssdat data setup before clkout 2.1 ns t hsdat data hold after clkout 0.8 ns switching characteristics t sclk clkout period 7.5 ns t sclkh clkout width high 2.5 ns t sclkl clkout width low 2.5 ns t dcad command, addr, data delay after clkout 2 2 command pins include: sras , scas , swe , sdqm, sms , sa10, scke. 6.0 ns t hcad command, addr, data hold after clkout 1 0.8 ns t dsdat data disable after clkout 6.0 ns t ensdat data enable after clkout 1.0 ns figure 13. sdram interface timing t hcad t hcad t dsdat t dcad t ssdat t dcad t ensdat t hsdat t sclkl t sclkh t sclk clkout data (in) data(out) cmnd addr (out) note: command = sras scas swe sm sms sa10 sce
rev. 0 | page 26 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 external port bus request and grant cycle timing table and figure describe external port bus request and bus grant operations table 19. external port bus re quest and grant cycle timing parameter 1 2 min max nit timing requirements t bs br asserted to clkout high setup 4.6 ns t bh clkout high to br deasserted hold time 0.0 ns switching characteristics t sd clkout low to xms , address, and rd /wr disable 4.5 ns t se clkout low to xms , address, and rd /wr enable 4.5 ns t dbg clkout high to bg high setup 3.6 ns t ebg clkout high to bg deasserted hold time 3.6 ns t dbh clkout high to bgh high setup 3.6 ns t ebh clkout high to bgh deasserted hold time 3.6 ns 1 these are preliminary timing parameters that are based on worst-case operating conditions. 2 the pad loads for these timi ng parameters are 20 pf. figure 14. external port bus request and grant cycle timing addr19-1 amsx clot bg awe bgh are br abe1-0 bh bs s se s s se se ebg bg t ebh bh
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 27 of 56 | march 2004 parallel peripheral interface timing table and figure on page describe parallel peripheral interface operations table 20. parallel peripheral interface timing parameter min max nit timing requirements t pclkw ppi_clk width 6.0 ns t pclk ppi_clk period 1 15.0 ns t sfspe external frame sync setup before ppi_clk 3.0 ns t hfspe external frame sync hold after ppi_clk 3.0 ns t sdrpe receive data setup before ppi_clk 2.0 ns t hdrpe receive data hold after ppi_clk 4.0 ns switching characteristics - gp output and frame capture modes t dfspe internal frame sync delay after ppi_clk 10.0 ns t hofspe internal frame sync hold after ppi_clk 0.0 ns t ddtpe transmit data delay after ppi_clk 10.0 ns t hdtpe transmit data hold after ppi_clk 0.0 ns 1 ppi_clk frequency cannot exceed f sclk /2 figure 15. gp output mode and frame capture timing t ddtpe t hdtpe ppi_clk ppi_fs1 ppix drive edge sample edge t sfspe t hfspe t pclkw t dfspe t hofspe ppi_fs2 t sdrpe t hdrpe
rev. 0 | page 28 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 serial ports table through table on page and figure on page through figure on page describe serial port operations table 21. serial portsexternal clock parameter min max nit timing requirements t sfse tfs/rfs setup before tsclk/rsclk 1 3.0 ns t hfse tfs/rfs hold after tsclk/rsclk 1 3.0 ns t sdre receive data setup before rsclk 1 3.0 ns t hdre receive data hold after rsclk 1 3.0 ns t sclkew tsclk/rsclk width 4.5 ns t sclke tsclk/rsclk period 15.0 ns 1 referenced to sample edge. table 22. serial portsinternal clock parameter min max nit timing requirements t sfsi tfs/rfs setup before tsclk/rsclk 1 8.0 ns t hfsi tfs/rfs hold after tsclk/rsclk 1 C2.0 ns t sdri receive data setup before rsclk 1 6.0 ns t hdri receive data hold after rsclk 1 0.0 ns t sclkew tsclk/rsclk width 4.5 ns t sclke tsclk/rsclk period 15.0 ns 1 referenced to sample edge. table 23. serial portsexternal clock parameter min max nit switching characteristics t dfse tfs/rfs delay after tsclk/rsclk (internally generated tfs/rfs) 1 10.0 ns t hofse tfs/rfs hold after tsclk/rsclk (internally generated tfs/rfs) 1 0.0 ns t ddte transmit data delay after tsclk 1 10.0 ns t hdte transmit data hold after tsclk 1 0.0 ns 1 referenced to drive edge. table 24. serial portsinternal clock parameter min max nit switching characteristics t dfs i tfs/rfs delay after tsclk/rsclk (internally generated tfs/rfs) 1 3.0 ns t hofs i tfs/rfs hold after tsclk/rsclk (internally generated tfs/rfs) 1 ? 1.0 ns t ddt i transmit data delay after tsclk 1 3.0 ns t hdt i transmit data hold after tsclk 1 ? 2.0 ns t sclkiw tsclk/rsclk width 4.5 ns 1 referenced to drive edge.
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 29 of 56 | march 2004 table 25. serial portsenable and three-state parameter min max nit switching characteristics t dtene data enable delay from external tsclk 1 0ns t ddtte data disable delay from external tsclk 1 10.0 ns t dteni data enable delay from internal tsclk 1 C2.0 ns t ddtti data disable delay from internal tsclk 1 3.0 ns 1 referenced to drive edge. table 26. external late frame sync parameter min max nit switching characteristics t ddtlfse data delay from late external tfs or external rfs with mce = 1, mfd = 0 1, 2 10.0 ns t dtenlfse data enable from late fs or mce = 1, mfd = 0 1,2 0ns 1 mce = 1, tfs enable and tfs valid follow t ddtenfs and t ddtlfse . 2 if external rfs/tfs setup to rsclk/tsclk t sclke /2, then t ddtlsck and t dtenlsck apply otherwise t ddtlfse and t dtenlfs apply.
rev. 0 | page 30 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 figure 16. serial ports dt dt t ddtte t dtene t ddtti t dteni drive edge drive edge drive edge drive edge tsclk / rsclk tsclk / rsclk tsclk (ext) tfs ("late", ext.) tsclk (int) tfs ("late", int.) t sdri rsclk rfs dr drive edge sample edge t hdri t sfsi t hfsi t dfse t hofse t sclkiw data receive- internal clock t sdre data receive- external clock rsclk rfs dr drive edge sample edge t hdre t sfse t hfse t dfse t sclkew t hofse note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge. t ddti t hdti tsclk tfs dt drive edge sample edge t sfsi t hfsi t sclkiw t dfsi t hofsi data transmit- internal clock t ddte t hdte tsclk tfs dt drive edge sample edge t sfse t hfse t dfse t sclkew t hofse data transmit- external clock note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge.
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 31 of 56 | march 2004 figure 17. external late frame sync (frame sync setup t sclke /2) t ddtlfse t sfse/i t hdte/i rsclk drive drive sample rfs dt 2nd bit 1st bit t ddtenfs t ddte/i t hofse/i t ddtenfs t sfse/i t hdte/i drive drive sample dt tsclk tfs 2nd bit 1st bit t ddtlfse t ddte/i t hofse/i external rfs with mce = 1, mfd = 0 late external tfs
rev. 0 | page 32 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 figure 18. external late frame sync (frame sync setup > t sclke /2) dt rsclk rfs t sfse/i t hofse/i t dtenlsck t ddte/i t hdte/i t ddtlsck drive sample 1st bit 2nd bit drive dt tsclk tfs t sfse/i t hofse/i t dtenlsck t ddte/i t hdte/i t ddtlsck drive sample 1st bit 2nd bit drive late external tfs external rfs with mce = 1, mfd = 0
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 33 of 56 | march 2004 serial peripheral interface (spi) port master timing table and figure describe spi port master operations table 27. serial peripheral interface (spi) portmaster timing parameter min max nit timing requirements t sspidm data input valid to sck ed ge (data input setup) 7.5 ns t hspidm sck sampling edge to data input invalid C1.5 ns switching characteristics t sdscim spiselx low to first sck edge (x=0 or 1) 2t sclk C1.5 ns t spichm serial clock high period 2t sclk C1.5 ns t spiclm serial clock low period 2t sclk C1.5 ns t spiclk serial clock period 4t sclk C1.5 ns t hdsm last sck edge to spiselx high (x= 0 or 1) 2t sclk C1.5 ns t spitdm sequential transfer delay 2t sclk C1.5 ns t ddspidm sck edge to data out valid (data out delay) 0 6 ns t hdspidm sck edge to data out invalid (data out hold) C1.0 4.0 ns figure 19. serial peripheral interface (spi) portmaster timing t sspidm t hspidm t hdspidm lsb msb t hspidm t ddspidm mosi (output) miso (input) spiselx otpt sc cpol 0 otpt sc cpol 1 otpt spichm spiclm spiclm spicl spichm hsm spitm hspim lsb ali lsb msb msb ali hspim spim mosi otpt miso ipt sspim cpha1 cpha0 msb ali sscim sspim lsb ali
rev. 0 | page 34 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 serial peripheral interface (spi) port slave timing table and figure describe spi port slave operations table 28. serial peripheral interface (spi) portslave timing parameter min max nit timing requirements t spichs serial clock high period 2t sclk C1.5 ns t spicls serial clock low period 2t sclk C1.5 ns t spiclk serial clock period 4t sclk C1.5 ns t hds last sck edge to spiss not asserted 2t sclk C1.5 ns t spitds sequential transfer delay 2t sclk C1.5 ns t sdsci spiss assertion to first sck edge 2t sclk C1.5 ns t sspid data input valid to sck ed ge (data input setup) 1.6 ns t hspid sck sampling edge to data input invalid 1.6 ns switching characteristics t dsoe spiss assertion to data out active 0 8 ns t dsdhi spiss deassertion to data high impedance 0 8 ns t ddspid sck edge to data out valid (data out delay) 0 10 ns t hdspid sck edge to data out invalid (data out hold) 0 10 ns figure 20. serial peripheral interface (spi) portslave timing t hspid t ddspid t dsdhi lsb msb msb valid t hspid t dsoe t ddspid t hdspid miso (output) mosi (input) t sspid spiss ipt sc cpol 0 ipt sc cpol 1 ipt ssci spichs spicls spicls spicl hs spichs sspi hspi shi lsb ali msb msb ali soe spi miso otpt mosi ipt sspi lsb ali lsb cpha1 cpha0 spits
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 35 of 56 | march 2004 universal asynchronous receiver-transmitter (uart) portreceive and transmit timing figure describes uart port receive and transmit operations the maximum baud rate is scl/ as shown in figure there is some latency between the generation internal uart interrupts and the external data operations these latencies are negligible at the data transmission rates for the uart figure uart portreceive and transmit timing rd data() iteral uart receie iterrupt uart receie bit set b data stop cleared b fifo read clout (sample cloc) td data() stop () iteral uart trasmit iterrupt uart trasmit bit set b program cleared b write to trasmit start stop trasmit receie
rev. 0 | page 36 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 programmable flags cycle timing table and figure describe programmable flag operations table 29. programmable flags cycle timing parameter min max nit timing requirements t wfi flag input pulse width t sclk + 1 ns switching characteristics t dfo flag output delay from clkout low 6 ns figure 22. programmable flags cycle timing flag input pf (input) t wfi pf (output) clkout flag output t dfo
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 37 of 56 | march 2004 timer cycle timing table and figure describe timer expired operations the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of f scl / mh table 30. timer cycle timing parameter min max nit timing characteristics t wl timer pulse width input low 1 (measured in sclk cycles) 1 sclk t wh timer pulse width input high 1 (measured in sclk cycles) 1 sclk switching characteristics t hto timer pulse width output 2 (measured in sclk cycles) 1 (2 32 C1) sclk 1 the minimum pulse widths apply for tmrx inpu t pins in width capture and external clock modes. they also apply to the pf1 or ppi _clk input pins in pwm output mode. 2 the minimum time for t hto is one cycle, and th e maximum time for t hto equals (2 32 C1) cycles. figure 23. timer pwm_out cycle timing clkout tmrx (pwm output mode) t hto tmrx (width capture and external clock modes) t wl t wh
rev. 0 | page 38 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 jtag test and emulation port timing table and figure describe jtag port operations table 31. jtag port timing parameter min max nit timing requirements t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setup before tck high 1 4ns t hsys system inputs hold after tck high 1 5ns t trstw trst pulse width 2 (measured in tck cycles) 4 tck switching characteristics t dtdo tdo delay from tck low 10 ns t dsys system outputs delay after tck low 3 012ns 1 system inputs=data15C0, ardy, tmr2C0, pf15 C0, ppi_clk, rsclk0C1, rfs0C1, dr0pri, dr0sec , tsclk0C1, tfs0C1, dr1pri, dr1sec, mosi , miso, sck, rx, reset , nmi, bmode1C0, br , pp3C0. 2 50 mhz maximum 3 system outputs=data15C0, addr19C1, abe1C0 , aoe , are , awe , ams3C0 , sras , scas , swe , scke, clkout, sa10, sms , tmr2C0, pf15C0, rsclk0C1, rfs0C1, tsclk0C1, tfs0C1, dt0pri, dt0sec, dt1pri, dt1sec, mosi, miso, sck, tx, bg , bgh , ppi3C0. figure 24. jtag port timing tms tdi tdo system inputs system outputs tck t tck t htap t stap t dtdo t ssys t hsys t dsys
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 39 of 56 | march 2004 output drive currents figure 25 through figure 32 show typical current-voltage char- acteristics for the output drivers of the adsp-bf531/2/3 processor. the curves represent the current drive capability of the output drivers as a function of output voltage. figure 25. drive current a (low v ddext ) figure 26. drive current a (high v ddext ) source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh v ol v ddext = 2.25v @ 95 c v ddext = 2.50v @ 25 c v ddext = 2.75v @ ?40 c source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 v oh v ddext = 2.95v @ 95 c v ddext = 3.30v @ 25 c v ddext = 3.65v @ ?40 c v ol figure 27. drive current b (low v ddext ) figure 28. drive current b (high v ddext ) source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh v ol v ddext = 2.25v @ 95 c v ddext = 2.50v @ 25 c v ddext = 2.75v @ ?40 c v oh v ddext = 2.95v @ 95 c v ddext = 3.30v @ 25 c v ddext = 3.65v @ ?40 c v ol source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 source current (ma)
rev. 0 | page 40 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 figure 29. drive current c (low v ddext ) figure 30. drive current c (high v ddext ) source current (ma) source voltage (v) 60 40 20 0 ?20 ?40 ?60 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh v ol v ddext = 2.25v @ 95 c v ddext = 2.50v @ 25 c v ddext = 2.75v @ ?40 c 60 80 40 20 0 ?20 ?40 ?60 ?80 ?100 source current (ma) v oh v ddext = 2.95v @ 95 c v ddext = 3.30v @ 25 c v ddext = 3.65v @ ?40 c v ol 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 source voltage (v) figure 31. drive current d (low v ddext ) figure 32. drive current d (high v ddext ) source current (ma) source voltage (v) 100 60 ?60 20 ?20 0 ?40 40 ?80 80 ?100 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh v ol v ddext = 2.25v @ 95 c v ddext = 2.50v @ 25 c v ddext = 2.75v @ ?40 c 150 100 50 0 ?50 ?100 ?150 source current (ma) v oh v ol 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 source voltage (v) v ddext = 2.95v @ 95 c v ddext = 3.30v @ 25 c v ddext = 3.65v @ ?40 c
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 41 of 56 | march 2004 power dissipation total power dissipation has two components: one due to inter- nal circuitry (p int ) and one due to the switching of external output drivers (p ext ). table 32 shows the power dissipation for internal circuitry (v ddint ). internal power dissipation is depen- dent on the instruction execution sequence and the data operands involved. the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: number of output pins (o) th at switch during each cycle maximum frequency (f) at which they can switch their load capacitance (c) their voltage swing (v ddext ) the external component is calculated using: the frequency f includes driving the load high and then back low. for example: data15C0 pins can drive high and low at a maximum rate of 1/(2 t sclk ) while in sdram burst mode. a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: note that the conditions causing a worst-case p ext differ from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from a ll ones (1s) to all zeros (0s). note, as well, that it is not common for an applica- tion to have 100% or even 50% of the outputs switching simultaneously. table 32. internal power dissipation 1 1 see ee-229 estimating power for adsp-bf533 blackfin processors. test conditions 2 2 i dd data is specified for typical process parameters. all data at 25c. parameter f cclk 50 m ddint 0.8 f cclk 400 m ddint 1.2 f cclk 500 m ddint 1.2 f cclk 600 m ddint 1.2 nit i ddtyp 3 3 processor executing 75% dual mac, 25% add with moderate data bus activity. 26 160 190 220 ma i ddsleep 4 4 see the adsp-bf53x blackfin processor hardware reference manual for defini- tions of slee and dee slee oerating modes 16 37 37 37 ma i dddeepsleep 4 14 31 31 31 ma i ddhibernate 5 5 measured at v ddext = 3.65v with voltage regulator off (v ddint = 0v). 50 a i ddrtc 6 6 measured at v ddrtc = 3.3v at 25oc. 30 a p ext oc v 2 dd f = p total p ext i dd v ddint () + =
rev. 0 | page 42 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 test conditions all timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving the output enable time t ea is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the output enable/disable diagram ( figure ) the time t eameasured is the interval from when the reference signal switches to when the output voltage reaches (output high) or (output low) time t trip is the interval from when the output starts driving to when the output reaches the or trip voltage time t ea is calculated as shown in the equation if multiple pins (such as the da ta bus) are enabled the measure- ment value is that of the first pin to start driving output disable time output pins are considered to be disabled when they stop driv- ing go into a high impedance state and start to decay from their output high or low voltage the time for the voltage on the bus to decay by ? ? ? example system hold time calculation to determine the data output hold time in a particular system first calculate t deca using the equation given above choose ? ? () () ( ) capacitive loading output delays and holds are based on standard capa citive loads pf on all pins (see figure ) figure through figure on page show how output rise time varies with capacitance the delay and hold specifications given should be derated by a factor derived from these figures the graphs in these figures may not be linear outside the ranges shown t ena t ena_measured t trip ? = t decay c l v ? () i l ? = figure 33. output enable/disable figure 34. equivalent device loading for ac measurements (includes all fixtures) figure 35. voltage reference levels for ac measurements (except output enable/disable) reference signal t dis output starts driving v oh (measured) v v ol (measured) + v t dis_measured v oh (measured) v ol (measured) 2.0v 1.0v v oh (measured) v ol (measured) high impedance state. test conditions cause this voltage to be approximately 1.5v. output stops driving t ena t decay t ena-measured t trip 1.5v 30pf to output pin 50 ohms input or output 1.5v 1.5v
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 43 of 56 | march 2004 figure 36. typical output delay or hold for driver a at evdd min figure 37. typical output delay or hold for driver a at evdd max abe_b[0] (133 mhz driver), evdd min = 2.25v, temperature = 85c load capacitance (pf) rise time rise and fall time ns (10%-90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time abe0 (133 mhz driver), evdd max = 3.65v, temperature = 85c load capacitance (pf) rise time rise and fall time ns (10%-90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time figure 38. typical output delay or hold for driver b at evdd min figure 39. typical output delay or hold for driver b at evdd max clkout (clkout driver), evdd min = 2.25v, temperature = 85c load capacitance (pf) rise time rise and fall time ns (10%-90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time clkout (clkout driver), evdd max = 3.65v, temperature = 85c load capacitance (pf) rise time rise and fall time ns (10%-90%) 10 9 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 fall time
rev. 0 | page 44 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 figure 40. typical output delay or hold for driver c at evdd min figure 41. typical output delay or hold for driver c at evdd max tmr0 (33 mhz driver), evdd min = 2.25v, temperature = 85c load capacitance (pf) rise time rise and fall time ns (10%-90%) 25 30 20 15 10 5 0 0 50 100 150 200 250 fall time tmr0 (33 mhz driver), evdd max = 3.65v, temperature = 85c load capacitance (pf) rise time rise and fall time ns (10%-90%) 20 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time figure 42. typical output delay or hold for driver d at evdd min figure 43. typical output delay or hold for driver d at evdd max sck (66 mhz driver), evdd min = 2.25v, temperature = 85c load capacitance (pf) rise time rise and fall time ns (10%-90%) 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time sck (66 mhz driver), evdd max = 3.65v, temperature = 85c load capacitance (pf) rise time rise and fall time ns (10%-90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 45 of 56 | march 2004 environmental conditions to determine the junction temperature on the application printed circuit board use: where: t j = junction temperature ( c) t case = case temperature ( c) measured by customer at top center of package. = =( ) =( c) in table 33 , airflow measurements comply with jedec stan- dards jesd51-2 and jesd51-6, and the junction-to-board measurement complies with je sd51-8. the junction-to-case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. thermal resistance table 33. thermal characteristics for bc-160 package parameter condition typical nit ja 0 linear m/s airflow 34.1 c/w jma 1 linear m/s airflow 30.1 c/w jma 2 linear m/s airflow 28.8 c/w jb not applicable 25.55 c/w jc not applicable 8.75 c/w jt 0 linear m/s airflow 0.13 c/w table 34. thermal characteristics for st-176-1 package parameter condition typical nit ja 0 linear m/s airflow 34.9 c/w jma 1 linear m/s airflow 33.0 c/w jma 2 linear m/s airflow 32.0 c/w jt 0 linear m/s airflow 0.50 c/w jt 1 linear m/s airflow 0.75 c/w jt 2 linear m/s airflow 1.00 c/w t j t case jt p d () + = t j t a ja p d () + = table 35. thermal characteristics for b-169 package parameter condition typical nit ja 0 linear m/s airflow 28.6 c/w jma 1 linear m/s airflow 24.6 c/w jma 2 linear m/s airflow 23.8 c/w jb not applicable 21.75 c/w jc not applicable 12.7 c/w jt 0 linear m/s airflow 0.78 c/w
rev. 0 | page 46 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 160-lead bga pinout table 36 lists the bga pinout by signal. table 37 on page 47 lists the bga pinout by ball number. table 36. 160-ball bga pin assignme nt (alphabetically by signal) signal ball no. signal ball no. signal ball no. signal ball no. abe0 h13 data12 m5 gnd l6 sck d1 abe1 h12 data13 n5 gnd l8 scke b13 addr1 j14 data14 p5 gnd l10 sms c13 addr10 m13 data15 p4 gnd m4 sras d13 addr11 m14 data2 p9 gnd m10 swe d12 addr12 n14 data3 m8 gnd p14 tck p2 addr13 n13 data4 n8 miso e2 tdi m3 addr14 n12 data5 p8 mosi d3 tdo n3 addr15 m11 data6 m7 nmi b10 tfs0 h3 addr16 n11 data7 n7 pf0 d2 tfs1 e1 addr17 p13 data8 p7 pf1 c1 tmr0 l2 addr18 p12 data9 m6 pf10 a4 tmr1 m1 addr19 p11 dr0pri k1 pf11 a5 tmr2 k2 addr2 k14 dr0sec j2 pf12 b5 tms n2 addr3 l14 dr1pri g3 pf13 b6 trst n1 addr4 j13 dr1sec f3 pf14 a6 tsclk0 j1 addr5 k13 dt0pri h1 pf15 c6 tsclk1 f1 addr6 l13 dt0sec h2 pf2 c2 tx k3 addr7 k12 dt1pri f2 pf3 c3 vddext a1 addr8 l12 dt1sec e3 pf4 b1 vddext c7 addr9 m12 emu m2 pf5 b2 vddext c12 ams0 e14 gnd a10 pf6 b3 vddext d5 ams1 f14 gnd a14 pf7 b4 vddext d9 ams2 f13 gnd b11 pf8 a2 vddext f12 ams3 g12 gnd c4 pf9 a3 vddext g4 aoe g13 gnd c5 ppi0 c8 vddext j4 ardy e13 gnd c11 ppi1 b8 vddext j12 are g14 gnd d4 ppi2 a7 vddext l7 awe h14 gnd d7 ppi3 b7 vddext l11 bg p10 gnd d8 ppi_clk c9 vddext p1 bgh n10 gnd d10 reset c10 vddint d6 bmode0 n4 gnd d11 rfs0 j3 vddint e4 bmode1 p3 gnd f4 rfs1 g2 vddint e11 br d14 gnd f11 rsclk0 l1 vddint j11 clkin a12 gnd g11 rsclk1 g1 vddint l4 clkout b14 gnd h4 rtxi a9 vddint l9 data0 m9 gnd h11 rtxo a8 vddrtc b9 data1 n9 gnd k4 rx l3 vrout0 a13 data10 n6 gnd k11 sa10 e12 vrout1 b12 data11 p6 gnd l5 scas c14 xtal a11
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 47 of 56 | march 2004 table 37 lists the bga pinout by ball number. table 36 on page 46 lists the bga pinout by signal. figure 44 lists the top view of the bga ball configuration. figure 45 lists the bottom view of the bga ball configuration. table 37. 160-ball bga pin assignment (numerically by ball number) ball no. signal ball no. signal ball no. signal ball no. signal a1 vddext c13 sms h1 dt0pri m3 tdi a2 pf8 c14 scas h2 dt0sec m4 gnd a3 pf9 d1 sck h3 tfs0 m5 data12 a4 pf10 d2 pf0 h4 gnd m6 data9 a5 pf11 d3 mosi h11 gnd m7 data6 a6 pf14 d4 gnd h12 abe1 m8 data3 a7 ppi2 d5 vddext h13 abe0 m9 data0 a8 rtxo d6 vddint h14 awe m10 gnd a9 rtxi d7 gnd j1 tsclk0 m11 addr15 a10 gnd d8 gnd j2 dr0sec m12 addr9 a11 xtal d9 vddext j3 rfs0 m13 addr10 a12 clkin d10 gnd j4 vddext m14 addr11 a13 vrout0 d11 gnd j11 vddint n1 trst a14 gnd d12 swe j12 vddext n2 tms b1 pf4 d13 sras j13 addr4 n3 tdo b2 pf5 d14 br j14 addr1 n4 bmode0 b3 pf6 e1 tfs1 k1 dr0pri n5 data13 b4 pf7 e2 miso k2 tmr2 n6 data10 b5 pf12 e3 dt1sec k3 tx n7 data7 b6 pf13 e4 vddint k4 gnd n8 data4 b7 ppi3 e11 vddint k11 gnd n9 data1 b8 ppi1 e12 sa10 k12 addr7 n10 bgh b9 vddrtc e13 ardy k13 addr5 n11 addr16 b10 nmi e14 ams0 k14 addr2 n12 addr14 b11 gnd f1 tsclk1 l1 rsclk0 n13 addr13 b12 vrout1 f2 dt1pri l2 tmr0 n14 addr12 b13 scke f3 dr1sec l3 rx p1 vddext b14 clkout f4 gnd l4 vddint p2 tck c1 pf1 f11 gnd l5 gnd p3 bmode1 c2 pf2 f12 vddext l6 gnd p4 data15 c3 pf3 f13 ams2 l7 vddext p5 data14 c4 gnd f14 ams1 l8 gnd p6 data11 c5 gnd g1 rsclk1 l9 vddint p7 data8 c6 pf15 g2 rfs1 l10 gnd p8 data5 c7 vddext g3 dr1pri l11 vddext p9 data2 c8 ppi0 g4 vddext l12 addr8 p10 bg c9 ppi_clk g11 gnd l13 addr6 p11 addr19 c10 reset g12 ams3 l14 addr3 p12 addr18 c11 gnd g13 aoe m1 tmr1 p13 addr17 c12 vddext g14 are m2 emu p14 gnd
rev. 0 | page 48 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 figure 44. 160-ball bga ball configuration (top view) figure 45. 160-ball bga ball configuration (bottom view) a b c d e f g h j k l m n p 1234567891011121314 v ddint v ddext gnd i/o key: v rout v ddrtc a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v ddint v ddext gnd i/o key: v rout v ddrtc
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 49 of 56 | march 2004 169-ball pbga pinout table38 lists the pbga pinout by signal. table39 on page52 lists the pbga pinout by ball number. table 38. 169-ball pbga pin assignme nt (alphabetically by signal) signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. abe [0] h16 data [13] t7 gnd g11 pf [8] b4 vdd k12 abe [1] h17 data [14] u6 gnd h7 pf [9] a4 vdd l12 addr [1] j16 data [15] t6 gnd h8 ppi [0] b9 vdd m10 addr [10] n16 data [2] u13 gnd h9 ppi [1] a9 vdd m11 addr [11] p17 data [3] t11 gnd h10 ppi [2] b8 vdd m12 addr [12] p16 data [4] u12 gnd h11 ppi [3] a8 vrout b12 addr [13] r17 data [5] u11 gnd j7 ppi_clk b10 vrout b13 addr [14] r16 data [6] t10 gnd j8 reset a12 xtal a13 addr [15] t17 data [7] u10 gnd j9 rfs0 n1 addr [16] u15 data [8] t9 gnd j10 rfs1 j1 addr [17] t15 data [9] u9 gnd j11 rsclk0 n2 addr [18] u16 dr0pr i m2 gnd k7 rsclk1 j2 addr [19] t14 dr0sec m1 gnd k8 rtcvdd f10 addr [2] j17 dr1pri h1 gnd k9 rtxi a10 addr [3] k16 dr1sec h2 gnd k10 rtxo a11 addr [4] k17 dt0pri k2 gnd k11 rx t1 addr [5] l16 dt0sec k1 gnd l7 sa10 b15 addr [6] l17 dt1pri f1 gnd l8 scas a16 addr [7] m16 dt1sec f2 gnd l9 sck d1 addr [8] m17 emu u1 gnd l10 scke b14 addr [9] n17 evdd b2 gnd l11 sms a17 ams [0] d17 evdd f6 gnd m9 sras a15 ams [1] e16 evdd f7 gnd t16 swe b17 ams [2] e17 evdd f8 miso e2 tck u4 ams [3] f16 evdd f9 mosi e1 tdi u3 aoe f17 evdd g6 nmi b11 tdo t4 ardy c16 evdd h6 pf [0] d2 tfs0 l1 are g16 evdd j6 pf [1] c1 tfs1 g2 awe g17 evdd k6 pf [10] b5 tmr0 r1 bg t13 evdd l6 pf [11] a5 tmr1 p2 bgh u17 evdd m6 pf [12] a6 tmr2 p1 bmode [0] u5 evdd m7 pf [13] b6 tms t3 bmode [1] t5 evdd m8 pf [14] a7 trst u2 br c17 evdd t2 pf [15] b7 tsclk0 l2 clkin a14 gnd b16 pf [2] b1 tsclk1 g1 clkout d16 gnd f11 pf [3] c2 tx r2 data [0] u14 gnd g7 pf [4] a1 vdd f12 data [1] t12 gnd g8 pf [5] a2 vdd g12 data [10] t8 gnd g9 pf [6] b3 vdd h12 data [11] u8 gnd g10 pf [7] a3 vdd j12
rev. 0 | page 50 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 table39 lists the pbga pinout by ball number. table38 on page 51 lists the pbga pinout by signal. table 39. 169-ball pbga pin assignme nt (numerically by ball number) ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal a1 pf 4 d16 clkout j2 rsclk1 m12 vdd u8 data 11 a2 pf 5 d17 ams 0 j6 evdd m16 addr 7 u9 data 9 a3 pf 7 e1 mosi j7 gnd m17 addr 8 u10 data 7 a4 pf 9 e2 miso j8 gnd n1 rfs0 u11 data 5 a5 pf 11 e16 ams 1 j9 gnd n2 rsclk0 u12 data 4 a6 pf 12 e17 ams 2 j10 gnd n16 addr 10 u13 data 2 a7 pf 14 f1 dt1pri j11 gnd n17 addr 9 u14 data 0 a8 ppi 3 f2 dt1sec j12 vdd p1 tmr2 u15 addr 16 a9 ppi 1 f6 evdd j16 addr 1 p2 tmr1 u16 addr 18 a10 rtxi f7 evdd j17 addr 2 p16 addr 12 u17 bgh a11 rtxo f8 evdd k1 dt0sec p17 addr 11 a12 reset f9 evdd k2 dt0pri r1 tmr0 a13 xtal f10 rtcvdd k6 evdd r2 tx a14 clkin f11 gnd k7 gnd r16 addr 14 a15 sras f12 vdd k8 gnd r17 addr 13 a16 scas f16 ams 3 k9 gnd t1 rx a17 sms f17 aoe k10 gnd t2 evdd b1 pf 2 g1 tsclk1 k11 gnd t3 tms b2 evdd g2 tfs1 k12 vdd t4 tdo b3 pf 6 g6 evdd k16 addr 3 t5 bmode 1 b4 pf 8 g7 gnd k17 addr 4 t6 data 15 b5 pf 10 g8 gnd l1 tfs0 t7 data 13 b6 pf 13 g9 gnd l2 tsclk0 t8 data 10 b7 pf 15 g10 gnd l6 evdd t9 data 8 b8 ppi 2 g11 gnd l7 gnd t10 data 6 b9 ppi 0 g12 vdd l8 gnd t11 data 3 b10 ppiclk g16 are l9 gnd t12 data 1 b11 nmi g17 awe l10 gnd t13 bg b12 vrout h1 dr1pri l11 gnd t14 addr 19 b13 vrout h2 dr1sec l12 vdd t15 addr 17 b14 scke h6 evdd l16 addr 5 t16 gnd b15 sa10 h7 gnd l17 addr 6 t17 addr 15 b16 gnd h8 gnd m1 dr0sec u1 emu b17 swe h9 gnd m2 dr0pri u2 trst c1 pf 1 h10 gnd m6 evdd u3 tdi c2 pf 3 h11 gnd m7 evdd u4 tck c16 ardy h12 vdd m8 evdd u5 bmode 0 c17 br h16 abe 0 m9 gnd u6 data 14 d1 sck h17 abe 1 m10 vdd u7 data 12 d2 pf 0 j1 rfs1 m11 vdd u8 data 11
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 51 of 56 | march 2004 176-lead lqfp pinout table 40 lists the lqfp pi nout by signal. table 41 on page 52 lists the lqfp pinout by lead number. table 40. 176-lead lqfp pin assignme nt (alphabetically by signal) signal lead no.signal lead no.signal lead no.signal lead no.signal lead no. abe0 151 data11 102 gnd 88 ppi_clk 21 vddext 71 abe1 150data12101gnd89ppi022vddext93 addr1 149 data13 100 gnd 90 ppi1 23 vddext 107 addr10 137 data14 99 gnd 91 ppi2 24 vddext 118 addr11 136 data15 98 gnd 92 ppi3 26 vddext 134 addr12 135 data2 114 gnd 97 reset 13 vddext 145 addr13 127 data3 113 gnd 106 rfs0 75 vddext 156 addr14 126 data4 112 gnd 117 rfs1 64 vddext 171 addr15 125 data5 110 gnd 128 rsclk0 76 vddint 25 addr16 124 data6 109 gnd 129 rsclk1 65 vddint 52 addr17 123 data7 108 gnd 130 rtxi 17 vddint 66 addr18 122 data8 105 gnd 131 rtxo 16 vddint 80 addr19 121 data9 104 gnd 132 rx 82 vddint 111 addr2 148 dr0pri 74 gnd 133 sa10 164 vddint 143 addr3 147 dr0sec 73 gnd 144 scas 166 vddint 157 addr4 146 dr1pri 63 gnd 155 sck 53 vddint 168 addr5 142 dr1sec 62 gnd 170 scke 173 vddrtc 18 addr6 141 dt0pri 68 gnd 174 sms 172 vrout1 5 addr7 140 dt0sec 67 gnd 175 sras 167 vrout2 4 addr8 139 dt1pri 59 gnd 176 swe 165 xtal 11 addr9 138 dt1sec 58 miso 54 tck 94 ams0 161 emu 83 mosi 55 tdi 86 ams1 160 gnd 1 nmi 14 tdo 87 ams2 159 gnd 2 pf0 51 tfs0 69 ams3 158 gnd 3 pf1 50 tfs1 60 aoe 154 gnd 7 pf10 34 tmr0 79 ardy 162 gnd 8 pf11 33 tmr1 78 are 153 gnd 9 pf12 32 tmr2 77 awe 152 gnd 15 pf13 29 tms 85 bg 119 gnd 19 pf14 28 trst 84 bgh 120 gnd 30 pf15 27 tsclk0 72 bmode0 96 gnd 39 pf2 49 tsclk1 61 bmode1 95 gnd 40 pf3 48 tx 81 br 163 gnd 41 pf4 47 vddext 6 clkin 10 gnd 42 pf5 46 vddext 12 clkout 169 gnd 43 pf6 38 vddext 20 data0 116 gnd 44 pf7 37 vddext 31 data1 115 gnd 56 pf8 36 vddext 45 data10 103 gnd 70 pf9 35 vddext 57
rev. 0 | page 52 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 table 41 lists the lqfp pino ut by lead number. table 40 on page 51 lists the lqfp pi nout by signal. table 41. 176-lead lqfp pin assignment (numerically by lead number) lead no. signal lead no. signal lead no .signal lead no.signal lead no.signal 1 gnd 41 gnd 81 tx 121 addr19 161 ams0 2 gnd 42 gnd 82 rx 122 addr18 162 ardy 3gnd43gnd83emu 123 addr17 163 br 4 vrout2 44 gnd 84 trst 124 addr16 164 sa10 5 vrout1 45 vddext 85 tms 125 addr15 165 swe 6 vddext 46 pf5 86 tdi 126 addr14 166 scas 7 gnd 47 pf4 87 tdo 127 addr13 167 sras 8 gnd 48 pf3 88 gnd 128 gnd 168 vddint 9 gnd 49 pf2 89 gnd 129 gnd 169 clkout 10 clkin 50 pf1 90 gnd 130 gnd 170 gnd 11 xtal 51 pf0 91 gnd 131 gnd 171 vddext 12 vddext 52 vddint 92 gnd 132 gnd 172 sms 13 reset 53 sck 93 vddext 133 gnd 173 scke 14 nmi 54 miso 94 tck 134 vddext 174 gnd 15 gnd 55 mosi 95 bmode1 135 addr12 175 gnd 16 rtxo 56 gnd 96 bmode0 136 addr11 176 gnd 17 rtxi 57 vddext 97 gnd 137 addr10 18 vddrtc 58 dt1sec 98 data15 138 addr9 19 gnd 59 dt1pri 99 data14 139 addr8 20 vddext 60 tfs1 100 data13 140 addr7 21 ppi_clk 61 tsclk1 101 data12 141 addr6 22 ppi0 62 dr1sec 102 data11 142 addr5 23 ppi1 63 dr1pri 103 data10 143 vddint 24 ppi2 64 rfs1 104 data9 144 gnd 25 vddint 65 rsclk1 105 data8 145 vddext 26 ppi3 66 vddint 106 gnd 146 addr4 27 pf15 67 dt0sec 107 vddext 147 addr3 28 pf14 68 dt0pri 108 data7 148 addr2 29 pf13 69 tfs0 109 data6 149 addr1 30 gnd 70 gnd 110 data5 150 abe1 31 vddext 71 vddext 111 vddint 151 abe0 32 pf12 72 tsclk0 112 data4 152 awe 33 pf11 73 dr0sec 113 data3 153 are 34 pf10 74 dr0pri 114 data2 154 aoe 35 pf9 75 rfs0 115 data1 155 gnd 36 pf8 76 rsclk0 116 data0 156 vddext 37 pf7 77 tmr2 117 gnd 157 vddint 38 pf6 78 tmr1 118 vddext 158 ams3 39 gnd 79 tmr0 119 bg 159 ams2 40 gnd 80 vddint 120 bgh 160 ams1
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 53 of 56 | march 2004 outline dimensions dimensions in figure 46 160-ball plastic ball grid array, mini-bga (bc-160) , figure 47 176-lead lqfp (st-176-1) and figure 48 169-ball plastic ball grid array, mini-bga (b-169) are shown in millimeters. figure 46. 160-ball plastic ball grid array, mini-bga (bc-160) top view 12.00 bsc sq ball a1 indicator detail a seating plane 1.70 max 0.40 nom (note 3) 0.55 0.50 0.45 ball diameter detail a bottom view a b c d e f g h j k l m n p 13 11 9 7 5 3 1 14 12 10 8 6 4 2 0.80 bsc ball pitch 10.40 bsc sq notes 1. dimensions are in millimeters. 2. complies with jedec registered outline mo-205, variation ae. 3. minimum ball height 0.25. a1 corner index area 0.12 max coplanarity 1.31 1.21 1.11
rev. 0 | page 54 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 figure 47. 176-lead lqfp (st-176-1) top view (pins down) pin 1 133 1 132 45 44 88 89 176 26.00 bsc sq 24.00 bsc sq 0.50 bsc lead pitch seating plane 0.08 max lead coplanarity detail a notes detail a 0.27 0.22 0.17 0.75 0.60 0.45 0.15 0.05 1.45 1.40 1.35 1. dimensions in millimeters 2. actual position of each lead is within 0.08 of its ideal position, when measured in the lateral direction. 3. center dimensions are nominal 1.60 max
adsp-bf531/adsp-bf532/adsp-bf533 rev. 0 | page 55 of 56 | march 2004 figure 48. 169-ball plastic ball grid array, mini-bga (b-169) side view top view a1 ball pad corner bottom view 16.00 bsc sq 19.00 bsc sq 1.00 bsc ball pitch 2.50 2.23 1.97 seating plane 0.70 0.60 0.50 0.40 min detail a ball diameter 0.20 max coplanarity a b c d e f g h j k l m n p r t u 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 notes 1. dimensions are in millimeters. 2. complies with jedec registered outline ms-034, variation aag-2 . 3. minimum ball height 0.40 detail a
rev. 0 | page 56 of 56 | march 2004 adsp-bf531/adsp-bf532/adsp-bf533 ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03728-0-3/04(0) ordering guide part number temperature range (ambient ) package description instruction rate (max) operating voltage adsp-bf533skbc600 0oc to 70oc chip scale package ball grid array (mini-bga) bc-160 600 mhz 1.2 v internal, 2.5 v or 3.3 v i/o adsp-bf533sbbc500 C40oc to 85oc chip scale package ball grid array (mini-bga) bc-160 500 mhz 1.2 v internal, 2.5 v or 3.3 v i/o adsp-bf533sbbz500 1 1 z = pb-free part. C40oc to 85oc plastic ball grid array (pbga) b-169 500 mhz 1.2 v internal, 2.5 v or 3.3 v i/o ADSP-BF532SBBC400 C40oc to 85oc chip scale package ball grid array (mini-bga) bc-160 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o adsp-bf532sbst400 C40oc to 85oc quad flatpack (lqfp) st-176-1 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o adsp-bf532sbbz400 1 C40oc to 85oc plastic ball grid array (pbga) b-169 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o adsp-bf531sbbc400 C40oc to 85oc chip scale package ball grid array (mini-bga) bc-160 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o adsp-bf531sbst400 C40oc to 85oc quad flatpack (lqfp) st-176-1 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o adsp-bf531sbbz400 1 C40oc to 85oc plastic ball grid array (pbga) b-169 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o

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